1. Field of Invention
The present invention relates to a method for manufacturing P-type metal oxide semiconductor (PMOS). More particularly, the present invention relates to a method for manufacturing a buried-channel PMOS.
2. Description of Related Art
Ever since a large number of complementary MOS (CMOS) transistors are used in very large scale integrated (VLSI) circuits, the fabrication of PMOS transistors are of growing importance in the semiconductor industry. An important factor in the design of PMOS transistors that may affect device performance is the manner in which the doping of polysilicon gate is carried out.
In the fabrication of CMOS transistor that centered upon the production of an N-type polysilicon gate, both the N-type MOS field effect transistor (nMOSFET) and the P-type MOS field effect transistor (pMOSFET) need to perform a P-channel implant. The P-channel implant is necessary for adjusting the channel so that a lower threshold voltage for the VLSI circuit can be obtained. Through the implant process, a buried-channel is formed in the pMOSFET device.
On the other hand, a dual gate type of CMOS transistor can be produced. Due to the N-type channel profile in the pMOSFET and the work function difference between the P-type (P.sup.+) polysilicon gate and the doped channel, the pMOSFET device has a surface channel.
Short-channel effect can easily occur in the aforementioned buried-channel pMOSFET device. For example, in an article published in IEEE Trans. Electron Devices, vol. ED-32, pp. 584-589, 1985 by Genda J. Hu et al with the title "Design tradeoff between surface and buried-channel FET's", the author has suggested that the buried-channel device has a lower threshold voltage and a worse turnoff characteristics than a surface-channel device. However, using N-doped (N.sup.+) polysilicon gate in the fabrication of both nMOSFET and pMOSFET is capable of saving up to two masking steps. In addition, a buried-channel device has a higher transconductance and higher drain current drivability than a surface-channel device. Hence, buried-channel pMOSFET is now gradually used in short-channel devices. Therefore, how to overcome short-channel effect in the design of deep-submicron buried-channel pMOSFET has become a major topic of research.
FIG. 1A is a cross-sectional view showing a buried-channel pMOSFET device 100, and FIG. 1B is a cross-sectional view showing a surface-channel pMOSFET device 150. As shown in FIGS. 1A and 1B, the buried-channel pMOSFET 100 has an N-doped polysilicon gate 100a while the surface-channel pMOSFET 150 has a P-doped (P.sup.+) polysilicon gate 150a. Moreover, in FIG. 1A, the buried-channel pMOSFET 100 has a P-type layer 100b implanted as a P-channel whose junction depth is X.sub.j.
FIG. 2 is a graph having two curves in it, one showing the relationship between dopant concentration versus depth from substrate surface for a buried-channel pMOSFET 100 as shown in FIG. 1A and the other showing the same relationship for a surface-channel pMOSFET 150 as shown in FIG. 1B, both under the same threshold voltage of -0.6V. As shown in FIG. 2, curve 200a shows the concentration profile of channel dopants (P-type dopants) in a buried-channel pMOSFET 100 while curve 200b shows the concentration profile of channel dopants (N-type dopants) in a surface-channel pMOSFET 150. Furthermore, curve 200a has an inflection point A at a depth of X.sub.j.
FIG. 3 is a graph having two curves, one showing the relationship between voltage potential versus vertical depth from substrate surface for a buried-channel pMOSFET 100 as shown in FIG. 1A and the other showing the same relationship for a surface-channel pMOSFET 150 as shown in FIG. 1B, both under the same gate to source voltage (V.sub.GS) of 0V and drain to source voltage (V.sub.DS) of -5V. As shown in FIG. 3, curve 300a is the distribution of electric potential for a buried-channel pMOSFET 100 while curve 300b is the distribution of electric potential for a surface-channel pMOSFET 150. Since there is a P-type layer 100b on the surface of a buried-channel pMOSFET 100, the potential well 310a of curve 300a remains buried inside the substrate unlike the potential well 310b of curve 300b, which is on the substrate surface. Therefore, conduction channel of a buried-channel device is formed inside the substrate, and consequently more vulnerable to short-channel effect than a surface-channel device.
From the above description, if short-channel effect of a submicron buried-channel device is to be reduced, the conduction channel is preferably as close to the substrate surface as possible. The best method to achieve a near-surface conduction channel is to form a very thin P-type layer just beneath the substrate surface. Therefore, a number of articles concerning how to form a shallow P-type layer are published. Examples include an article published by T. Yoshitomi et al in Proceedings of 1993 VLSI Symp. on VLSI Tech., pp. 90-99 with the title of "Ultra-shallow buried-channel pMOSFET with extremely high transconductance", another article published by H. Matsuhashi et al in Proceedings of 1996 VLSI Symp. on VLSI Tech., pp. 36-37 with the title of "High-performance double-layer epitaxial-channel PMOSFET compatible with a single gate CMOSFET", and yet another article published by B. Lee et al in U.S. Pat. No. 5,266,510 having the title of "High performance sub-micron p-channel transistor with germanium implant".
In general, the techniques and method mentioned in the above published articles and patent require complicated processing and stringent controlling factors. Only the low-energy boron implantation technique suggested by T. Yoshitomi et al in his article is somewhat mature and can be carried out in the present-day CMOS fabrication environment. However, a low-energy boron implant has a rather low throughput and is therefore not quite cost effective.
In light of the foregoing, there is a need an improved method for forming a buried-channel pMOSFET device.